2012.12.06 10:05:40 (276613366418636800) from Daniel J. Bernstein, replying to "BeagleBoard.org (@beagleboardorg)" (276481714094747648):
@beagleboardorg I'm looking at what seems to be pure NEON code fitting easily into the Sitara data cache and instruction cache.
2012.12.05 11:20:58 (276269928133308416) from Daniel J. Bernstein:
Did TI tweak the Cortex A8 CPU cores in its Sitara SoC (BeagleBone etc.)? I'm seeing some small but repeatable performance differences.
2012.12.06 01:22:32 (276481714094747648) from "BeagleBoard.org (@beagleboardorg)":
@hashbreaker A lot of performance comes from busses, memory interface, cache, configuration, etc. Not all SoCs are equal.